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| PLL103-01 Low Skew Buffers FEATURES * * * * * * * * * * Generate 18 copies of High-speed clock inputs. Supports up to four SDRAM DIMMS synchronous clocks. Supports 2-wire I2C serial bus interface with readback. 50% duty cycle with low jitter. Less than 5ns delay. Skew between any outputs is less than 250 ps. Tri-state pin for testing. Frequency up to 133 MHZ. 3.0V-3.7V Supply range. 48-pin SSOP package. PIN CONFIGURATION N/C N/C VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN VDD SDRAM4 SDRAM5 GND VDD SDRAM6 SDRAM7 GND VDD SDRAM16 GND VDD1 SDATA 1 2 3 4 5 6 7 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N/C N/C VDD SDRAM15 SDRAM14 GND VDD SDRAM13 SDRAM12 GND OE^ VDD SDRAM11 SDRAM10 GND VDD SDRAM9 SDRAM8 GND VDD SDRAM17 GND GND1 SCLK PLL103-01 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BLOCK DIAGRAM SDRAM0 SDATA SCLK I2C Control SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 BUF_IN SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17 OE Note: ^: pull up POWER GROUP * * VDD: SDRAM( 0:17 ) VDD1: I2C Circuitry GROUND GROUP * * GND: SDRAM( 0:17 ) GND1: I2C Circuitry KEY SPECIFICATIONS * * * * BUFIN to SDRAM outputs Delay: 1 ~ 5 ns. Output Slew: 1.5 V/ns. Output Skew: 250 ps. Output Duty Cycle: 50% 5%. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 1 PLL103-01 Low Skew Buffers PIN DESCRIPTIONS Name SDRAM (0:3) SDRAM (4:7) SDRAM (8:11) SDRAM (12:15) SDRAM (16:17) OE BUF_IN SDATA SCLK VDD VDD1 GND GND1 N/C Number 4,5,8,9 13,14,17,18 31,32,35,36 40,41,44,45 21,28 38 11 24 25 3,7,12,16,20,2 9,33,37,42,46 23 6,10,15,19,22, 27,30,34,39,43 26 1,2,47,48 Type O O O O O I I B I P P P P SDRAM Byte0 Clock outputs. SDRAM Byte1 Clock outputs. SDRAM Byte2 Clock outputs. SDRAM Byte3 Clock outputs. SDRAM Byte4 Clock outputs. Description Tristates all outputs, active low. Has internal pull-up. Input for fanout buffers SDRAM (0:17). Serial data inputs for serial interface port. 3.3V Power supply for SDRAM buffer. 3.3V Power supply for I2C circuitry. Ground for SDRAM buffer. Power supply for I2C circuitry. Pins are internally disconnected. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 2 PLL103-01 Low Skew Buffers I2C BUS CONFIGURATION SETTING Address Assignment Slave Receiver/Transmitter Data Transfer Rate A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W _ Provides both slave write and readback functionality Standard mode at 100kbits/s This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09). Data Protocol I2C CONTROL REGISTERS 1. BYTE 0: SDRAM(0:7) Clock Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 18 17 14 13 9 8 5 4 Default 1 1 1 1 1 1 1 1 Description SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 3 PLL103-01 Low Skew Buffers 2. BYTE 1: SDRAM(8:15) Clock Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 45 44 41 40 36 35 32 31 Default 1 1 1 1 1 1 1 1 Description SDRAM15 (Active/Inactive) SDRAM14 (Active/Inactive) SDRAM13 (Active/Inactive) SDRAM12 (Active/Inactive) SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) 3. BYTE 2: SDRAM(16:17) Clock Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 28 21 - Default 1 1 1 1 1 1 1 1 Description SDRAM17 (Active/Inactive) SDRAM16 (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 4 PLL103-01 Low Skew Buffers ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature SYMBOL V DD VI VO TS TA MIN. V SS -0.5 V SS -0.5 V SS -0.5 -65 0 MAX. 7.0 V DD +0.5 V DD +0.5 150 70 UNITS V V V C C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC/DC Electrical Specifications PARAMETERS Input High Current Input Low Current Input High Voltage Input Low Voltage Input Frequency Input Capacitance SYMBOL I IH I IL I IL V IH V IL F IN C IN I DD1 I DD2 V IN = V DD CONDITIONS MIN. TYP. MAX. 5 UNITS uA uA uA V IN =0V; with no pull-up resistors V IN =0V; with 100k pull-up resistors 2 VSS-0.3 V DD =3.3V; All outputs loaded Logic Inputs C L = 0pf @ 66MHz C L = 0pf @ 100MHz C L = 30pf; RS= 33 @ 66MHz C L = 30pf; RS= 33 @ 100MHz Stopped, input at 0 or VDD 80 120 180 240 10 VDD+0.3 0.8 150 5 120 180 260 360 500 V V Mhz PF mA mA mA mA uA Operating Supply Current I DD3 I DD4 I DD5 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 5 PLL103-01 Low Skew Buffers 2. Output Buffer Electrical Specifications Unless otherwise stated, all power supplies = 3.3V5%, and ambient temperature range TA= 0C to 70C PARAMETERS Output High Voltage Output Low Voltage Output High Current Output Low Current Output Impedance Output Impedance Rise Time Fall Time Skew Duty Cycle SYMBOL V OH V OL I OH I OL R DSP R DSN Tr Tf Tskew DT TPROP CONDITIONS I OH = -36 mA I OH = 23 mA V OH = 2.0 V V OL = 0.8 V V O = (0.5) V DD V O = (0.5) V DD V OL = 0.4 V, V OH = 2.4V V OH = 2.4 V, V OL = 0.4V V T = 1.5 V V T = 1.5 V V T = 1.5 V V T = 1.5 V V T = 1.5 V MIN. 2.4 TYP. 3 0.27 -115 MAX. UNITS V 0.4 -54 V mA mA 40 10 10 57 24 24 0.95 0.95 110 1.33 1.33 250 55 6 8 8 ohm ohm ns ns ps % ns ns ns 45 1 1 1 50 5 Propagation TPROPEN TPROPDIS 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 6 PLL103-01 Low Skew Buffers PACKAGE INFORMATION 0.400 - 0.410 10.160 - 10.414 0.292 - 0.299 7.417 - 7.959 0.008 - 0.0135 0.203 - 0.343 0.025 0.835 0.015 (0.381) 0.010 - 0.016 (0.25 - 0.41) 45 0 0.620 - 0.630 (15.75 - 16.00) 0.088 - 0.096 (2.250 - 2.450) 0.097 - 0.104 (2.467 - 2.642) 30-6 0 0.050 MIN (1.346) 0.008 - 0.016 (0.20 - 0.41) 48PIN SSOP ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL103-01 X C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 7 |
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